1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device.
2. Discussion of the Related Art
Flash memory, a nonvolatile semiconductor memory, has received much attention in the semiconductor memory industry recently because flash memory is expected to replace the hard disk drive (HDD), which is an external storage that is currently the most widely used type in computer systems. For cache memory and the main storage of a computer, SRAM and DRAM electronically enabling reading/writing are currently used. However, they are volatile and lose stored data when power is off. Consequently, computer systems require additional external nonvolatile memory.
Presently, for external storage disks such as HDD, or magnetic memory such as magnetic tape primarily are used. However, magnetic memories are heavy, slow data readers, large power consumers, subject to external impacts, and difficult to miniaturize. Prior to flash memory, only magnetic memory was capable of enabling electrical reading/writing and was less expensive than EEPROMs, a nonvolatile memory.
With the flash memory capable of electrical reading/writing and much cheaper than the conventional EEPROM, and with gradually widely distributed portable computers requiring miniaturization, weight reduction, low power consumption, and high impact-resistance, there has been a worldwide trend to replace HDD with flash memory. System makers are currently using PCMCIA flash memory cards for auxiliary HDD memory while using the conventional HDD for personal computer systems because HDD and flash memory have a large difference in cost. However, if 64M flash memory is produced in mass quantities, the cost difference between the flash memory and HDD will be reduced below one-third of the present difference. Consequently, PCMCIA flash memory card will be used, instead of HDD, for the main external storage of portable computers. Besides, the flash memory will be used as a storage in a variety of applications such as in communication equipment including telephones, pagers, facsimiles, LANs, televisions, VCRs, game machines, cameras, audio players, car components, military electronic equipment, and medical instruments.
An EEPROM of the conventional memory device will be explained with reference to the attached drawings.
FIG. 1 shows a circuit configuration of a conventional EEPROM, and specifically, a unit cell of INTEL's ETOX flash EEPROM, which is one of the most typical flash EEPROMs.
A general EEPROM cell is made in the floating-gate avalanche-injection metal oxide semiconductor (FAMOS) configuration having a stacked gate MOSFET. The respective cell's control gate C.G is connected to a single wordline W/L, drain D is connected to a single bitline B/L, and source S is connected to a single common source line C.S.
Bitline B/L is connected to one input port of a sense AMP SA. The other input port of the sense AMP is coupled to a reference voltage V.sub.ref. The structure of the general EEPROM cell is shown in FIG. 2.
Referring to FIG. 2, floating gate F.G and control gate C.G are stacked sequentially on P-type silicon substrate 1. Source S and drain D are formed of N-type impurity regions on substrate 1 at both sides of floating gate F.G. Here, an insulating layer is formed between substrate 1 and floating gate F.G and between the floating gate and control gate C.G. Between floating gate F.G and control gate C.G, the insulating layer is formed as thick as the gate insulating layer of a general transistor. Between floating gate F.G and silicon substrate 1, a tunnel oxide layer is formed below 100 .ANG..
The operation of the conventional flash EEPROM will be described below. FIG. 3 shows the writing of data in the conventional EEPROM, and FIG. 4 shows the erasure of data in the conventional EEPROM.
To write data "1" in a cell, as shown in FIG. 3, a voltage of 7-8V is applied to bitline B/L corresponding to the cell, and a voltage pulse of 12-13V is applied to wordline W/L (control gate). Source S and the substrate are grounded. In this situation, avalanche breakdown is caused at the PN junction between drain D and the substrate, producing hot electrons. Some of the hot electrons obtain an energy larger than the energy barrier (about 3.2 eV) between the substrate and tunnel oxide layer, and enter floating gate F.G via the tunnel oxide layer from the substrate to be stored therein. This method is called channel hot electron injection.
Here, as the number of electrons stored in floating gate F.G increases, the cell's threshold voltage increases. Therefore, writing is performed so that generally the cell's threshold voltage becomes greater than 7V. Once the electrons are accumulated in floating gate F.G, the natural electron emission rate is sufficiently small to be ignored. Therefore, the number of accumulated electrons is maintained constant for years because the energy barrier between floating gate F.G and the insulating layer completely surrounding the floating gate is greater than 3eV. This state of the cell indicates logic "1" in binary.
The erasure data written in a cell will now be explained as follows.
As shown in FIG. 4, the substrate and control gate C.G are grounded, the drain is floated, and a voltage pulse of 12-13V is applied to a common source line C.S. Due to Fowler-Nordheim tunnelling, electrons accumulated in floating gate F.G are induced to source S via a thin gate oxide layer. Here, as the quantity of emitted electrons from the floating gate F.G increases, the cell's threshold voltage gradually decreases. In this manner, erasure is continued until the cell's threshold voltage is below 3V. This state indicates logic "0" in binary.
The reading of data accumulated in a cell will now be described.
A voltage of 1-2V is applied to bitline B/L connected to cell's drain D, and the substrate and source S are grounded. A voltage pulse of 3-5V is applied to wordline W/L connected to cell's control gate C.G. Here, if a "1" is stored in the cell, the cell is OFF so the charges stored in bitline B/L are not emitted, thereby maintaining the previously applied voltage of 1-2V.
If a "0" is stored in the cell, the cell is ON so the charges stored in bitline B/L are emitted to ground. Such a potential difference of bitline B/L is recognized by sense AMP SA of FIG. 1 connected to bitline B/L so that data accumulated in the cell is read.
In the conventional ETOX flash EEPROM, random access is enabled in data reading, and data reading time is relatively short. Despite those advantages, the conventional ETOX flash EEPROM has many drawbacks to solve. Some of the drawbacks will now be explained.
First, when data is stored in the cell the control gate and substrate are grounded, and a high voltage of 13V is applied to the source so that a voltage is not externally applied to the drain. Thus, there is a large voltage difference between the source and substrate. In the source junction, band-to-band tunneling and avalanche breakdown are caused. Accordingly, many pairs of electron-valence electron are produced at the source junction. Some of the pairs are accelerated by an electric field at a deep depletion region formed at the source junction so that they become valence electrons with high energies (hot holes) and are implanted into the tunnel oxide layer. Some are captured by the gate oxide layer. These captured valence electrons increase tunneling rate in erasing.
For this reason, the erasing threshold voltage of the cells in which valence electrons are captured in the tunnel oxide layer becomes sharply lower than that of usual cells in which valence electrons are not captured in the gate oxide layer. As a result, the erasing threshold voltage may be negative. In this case, leakage current flows through the cells, thereby causing errors in data reading. This is called overerasing.
Bad bits whose threshold voltage becomes too low after erasure due to valence electron capture in the gate oxide layer do not always remain as bad bits. Considerable numbers of the bad bits return to normal cells because valence electrons held by the tunnel oxide layer are lost by recombining with electrons passing through the tunnel oxide layer in later erasures. However, as the cycle of program/erasure proceeds, some initially normal cells become bad.
As explained above, one cannot predict when or in which of the cells the capture of valence electrons in the gate oxide layer will occur. For this reason, devices which may cause this problem cannot be checked in a screening test performed after the fabrication process.
In order to reduce such overerasing, as shown in FIGS. 3 and 4, the conventional ETOX flash EEPROM is made so that the source junction is a deep graded junction, thereby reducing hot holes in erasure. Even in this case, the hot holes cannot be prevented completely. In addition, the deeply formed source junction increases the area of the unit cell.
Secondly, in programming a cell, the wordlines of other unselected cells coupled to the bitline of the programmed cell are grounded. A voltage of about 7 to 8V is applied to the drain. Among the unselected cells, previously programmed cells have electrons stored in the floating gate so that the potential of the floating gate becomes about -2 to -3V.
Between the drain and floating gate of unselected but previously programmed cells, a large voltage difference of about 9-10V is formed so that the electrons of the floating gate are emitted to the drain, or hot holes produced at the drain junction are implanted into the floating gate, according to Fowler-Nordheim tunnelling. Consequently, lost electrons are stored in the floating gate.
Thirdly, the conventional ETOX flash EEPROM performs programming using the channel hot electron injection. When programming is performed using this method, a high voltage of about 6-8V is applied to a bitline coupled to a cell selected for programming. About 100 .mu.A of current flows through the bitline. This consumes a large amount of power in programming.